1 of 10 112006 features ? upgrade and drop-in replacement for ds2400 ? extended 2.8 to 6.0 voltage range ? multiple ds2401s can reside on a common 1-wire ? net ? unique, factory-lasered and tested 64-bit registration number (8-bit family code + 48- bit serial number + 8-bit crc tester); guaranteed no two parts alike ? built-in multidrop controller ensures compatibility with other 1-wire net products ? 8-bit family code specifies ds2401 communications requirements to reader ? presence pulse acknowledges when the reader first applies voltage ? low-cost to-92, sot-223, and tsoc surface mount packages ? reduces control, address, data, and power to a single pin ? zero standby power required ? directly connects to a single port pin of a microprocessor and communicates at up to 16.3kbits/s ? to-92 tape & reel version with leads bent to 100mil spacing (default) or with straight leads (ds2401t-sl) ? applications ? pcb identification ? network node id ? equipment registration ? operates over industria l temperature range of -40c to +85c pin assignment 1 2 0 1rrd flip chip, top view with laser mark, contacts not visible. ?rrd? = revision/date see 56-g7009-001 for package outline. pin description to-92, sot-223 tsoc flip chip pin 1 ground ground data (dq) pin 2 data (dq) data (dq) ground pin 3 no connect no connect ? pin 4 ground no connect ? pin 5-6 ? no connect ? ds2401 silicon serial numbe r www.maxim-ic.com top view see mech. drawings section top view 3.7mm x 4.0mm x 1.5mm bottom view to-92 dallas ds2401 2 3 1 1 2 3 1-wire is a registered trademark of dallas semiconductor. tsoc package
ds2401 2 of 10 ordering information standard lead-free description ds2401 ds2401+ to-92 package ds2401/t&r ds2401+t&r to-92 package, tape-and-reel ds2401/t&r/sl ds2401-sl+t&r to-92 package with straight leads, tape-and-reel ds2401z ds2401z+ sot-223 surface-mount package ds2401z/t&r ds2401z+t&r sot-223 surf ace-mount package, tape-and-reel ds2401p ds2401p+ tsoc surface-mount package ds2401p/t&r ds2401p+t&r tsoc surface-mount package, tape-and-reel DS2401X1 ? flip-chip package, tape & reel description the ds2401 enhanced silicon serial number is a low- cost, electronic registra tion number that provides an absolutely unique identity which can be determin ed with a minimal electroni c interface (typically, a single port pin of a microcontroller). the ds2401 consists of a factory-la sered, 64-bit rom that includes a unique 48-bit serial number, an 8-bit crc, and an 8-bi t family code (01h). data is transferred serially via the 1-wire protocol that requ ires only a single data lead and a ground return. power for reading and writing the device is derived from the data line itsel f with no need for an external power source. the ds2401 is an upgrade to the ds2400. the ds2401 is fully reverse-compatible with the ds2400 but provides the additional multi-drop capability that enab les many devices to reside on a single data line. the familiar to-92, sot-223 or tsoc package provi des a compact enclosure that allows standard assembly equipment to handle the device easily. operation the ds2401?s internal rom is accessed via a single data line. the 48-bit serial number, 8-bit family code and 8-bit crc are retrieved using the dallas 1-wire protocol. this protocol defines bus transactions in terms of the bus state during specified time slots th at are initiated on the falling edge of sync pulses from the bus master. all data is read and written least significant bit first. 1-wire bus system the 1-wire bus is a system which has a single bus mast er system and one or more slaves. in all instances, the ds2401 is a slave device. the bus master is typi cally a microcontroller. th e discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1-wire signaling (signal type and timing). hardware configuration the 1-wire bus has only a si ngle line by definition; it is important that each devi ce on the bus be able to drive it at the appropriate time. to facilitate this, each device attached to the 1-wire bus must have an open-drain connection or 3- state outputs. the ds2401 is an open-dr ain part with an internal circuit equivalent to that shown in figure 2. the bus master can be the same equivalent ci rcuit. if a bidirectional pin is not available, separate output and input pins can be tied togeth er. the bus master requires a pullup resistor at the master end of the bus , with the bus master circuit equiva lent to the one shown in figure 3. the value of the pullup resistor should be approximately 5k for short line lengths. a multidrop bus consists of a 1-wire bus with multiple slaves att ached. the 1-wire bus has a maximum data rate of 16.3kbits per second. the idle state for the 1-wire bus is high. if, for any reason, a transac tion needs to be suspended, the bus must be left in the idle state if th e transaction is to resume. if this doe s not occur and the bus is left low for more than 120 s, one or more of the devices on the bus may be reset.
ds2401 3 of 10 ds2401 memory map figure 1 8-bit crc code 48-bit serial number 8-bit family code (01h) msb lsb msb lsb msb lsb ds2401 equivalent circuit figure 2 bus master circuit figure 3 a) open drain note: depending on the 1-wire communication speed and the bus load characteristics, the optimal pullup resistor (r pu ) value will be in the 1.5k to 5k range. to data connection of ds2401 b) standard ttl to data connection of ds2401 see note see note
ds2401 4 of 10 transaction sequence the sequence for accessing the ds2401 via the 1-wire port is as follows: ? initialization ? rom function command ? read data initialization all transactions on the 1-wire bus begin with an initialization se quence. the initialization sequence consists of a reset pulse transmitted by the bus mast er followed by a presence pulse(s) transmitted by the slave(s). the presence pulse lets the bus ma ster know that the ds2401 is on the bus and is ready to operate. for more details, see the 1-wire signaling section. rom function commands once the bus master has detected a presence, it can issue one of the four rom function commands. all rom function commands are 8 bits long. a list of these commands follo ws (refer to flowchart in figure 4). read rom [33h] or [0fh] this command allows the bus master to read the ds2401?s 8-bit family code, unique 48-bit serial number, and 8-bit crc. this command can only be used if there is a single ds2401 on the bus. if more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wi red-and result). the ds2401 read ro m function will occur with a command byte of either 33h or 0fh in order to ensure compatibility with the ds2400, which will only respond to a 0fh command word with its 64-bit rom data. match rom [55h] / skip rom [cch] the complete 1-wire protocol for all dallas semiconductor i buttons contains a match rom and a skip rom command. since the ds2401 cont ains only the 64-bit rom with no additional data fields, the match rom and skip rom are not applicable and will cause no further activity on the 1-wire bus if executed. the ds2401 does not interfer e with other 1-wire pa rts on a multidrop bus that do respond to a match rom or skip rom (for example, a ds2401 and ds1994 on the same bus). search rom [f0h] when a system is initially brought up, the bus mast er might not know the number of devices on the 1- wire bus or their 64-bit rom codes. the search ro m command allows the bus master to use a process of elimination to identify the 64 -bit rom codes of all slave devices on the bus. the rom search process is the repetition of a simple 3-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. the bus master performs th is simple 3-step routine on each bit of the rom. after one complete pass, the bus master knows the contents of the rom in one device. the remaining number of devices and their rom codes ma y be identified by additional passes. see application note 187: 1-wire search algorithm for a comprehensive discussion of a rom search, including an actual example.
ds2401 5 of 10 1-wire signaling the ds2401 requires a strict protocol to ensure data integrity. the prot ocol consists of four types of signaling on one line: reset sequence with reset pulse a nd presence pulse, write 0, write 1, and read data. all these signals except presence pulse are initiated by the bus master. the initialization sequence required to begin any co mmunication with the ds2401 is shown in figure 5. a reset pulse followed by a presence pulse indicates the ds2401 is ready to send or receive data given the correct rom command. the bus master transmits (t x ) a reset pulse (t rstl , minimum 480 s). the bus master then releases the line and goes into receive mode (r x ). the 1-wire bus is pulled to a high state via the 5k pullup resistor. after detecting the rising edge on the data pin, the ds2401 waits (t pdh , 15-60 s) and then transmits the presence pulse (t pdl , 60-240 s). the 1-wire bus requires a pullup resistor range of 1.5k to 5k , depending on bus load characteristics. read/write time slots the definitions of write and read time slots are illust rated in figure 6. all time slots are initiated by the master driving the data line low. the falling edge of the data line synchronizes the ds2401 to the master by triggering a delay circuit in the ds2401. during write time slots, the delay circuit determines when the ds2401 will sample the data line. for a read data time sl ot, if a ?0? is to be tr ansmitted, the delay circuit determines how long the ds2401 will ho ld the data line low overriding the ?1? generated by the master. if the data bit is a 1, the ds2401 will l eave the read data time slot unchanged.
ds2401 6 of 10 rom functions flow chart figure 4
ds2401 7 of 10 initialization procedure ?r eset and prese nce pulses? figure 5 480 s t rstl < * 480 s t rsth < (includes recovery time) 15 s t pdh < 60 s 60 s t pdl < 240 s ? in order not to mask interrupt signali ng by other devices on the 1-wire bus, t rstl + t r should always be less than 960 s. read/write timing diagram figure 6 write-one time slot 60 s t slot < 120 s 1 s t low1 < 15 s 1 s t rec < resistor master resistor master ds2401
ds2401 8 of 10 read/write timing diagram (cont?d) figure 6 write-zero time slot 60 s t low0 < t slot < 120 s 1 s t rec < read-data time slot 60 s t slot < 120 s 1 s t lowr < 15 s 0 t release < 45 s 1 s t rec < t rdv = 15 s t su < 1 s crc generation to validate the data transmitted from the ds2401, the bus master may generate a crc value from the data as it is received. this generated value is compar ed to the value stored in the last 8 bits of the ds2401. if the two crc values match, the transmission is error-free. the equivalent polynomial func tion of this crc is: crc = x 8 + x 5 + x 4 + 1. additional information about the dallas 1-wire crc is available in application note 27 . custom ds2401 customization of a portion of the unique 48-bit seri al number by the customer is available. dallas semiconductor will register and assign a specific customer id in the 12 most significant bits of the 48-bit field. the next most significant bits are selectable by the customer as a starting value, and the least significant bits are non-selectable and will be auto matically incremented by one. certain quantities and conditions apply for these custom parts. contact your dallas semiconductor sales representative for more information. resistor master ds2401
ds2401 9 of 10 absolute maxi mum ratings* voltage on any pin relative to ground -0.5v to +7.0v operating temperature range -40 c to +85 c storage temperature range -55 c to +125 c soldering temperature see j-std-020a specification ? this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation se ctions of this specification is not implied. exposure to absolute maximum rating conditions for extended pe riods of time may affect reliability. dc electrical characteristics (-40 c to +85 c; v pup = 2.8v to 6.0v) parameter symbol min typ max units notes logic 1 v ih 2.2 v cc +0.3 v 1,6 logic 0 v il -0.3 +0.3 v 1 output logic low @ 4 ma v ol 0.4 v 1 output logic high v oh v pup 6.0 v 1,2 input load current i l 5 a 3 operating charge q op 30 nc 7,8 capacitance (t a = +25 c) parameter symbol min typ max units notes i/o (1-wire) c in/out 800 pf 9 ac electrical characteristics (-40c to +85c; v pup = 2.8v to 6.0v) parameter symbol min typ max units notes time slot t slot 60 120 s write 1 low time t low1 1 15 s 12 write 0 low time t low0 60 120 s read data valid t rdv 15 s 11 release time t release 0 15 45 s read data setup t su 1 s 5 recovery time t rec 1 s reset time high t rsth 480 s 4 reset time low t rstl 480 960 s 10 presence detect high t pdh 15 60 s presence detect low t pdl 60 240 s
ds2401 10 of 10 notes: 1) all voltages are referenced to ground. 2) v pup = external pullup voltage. 3) input load is to ground. 4) an additional reset or communication sequence ca nnot begin until the reset high time has expired. 5) read data setup time refers to the time the host must pull the 1-wire bus low to read a bit. data is guaranteed to be valid within 1 s of this falling edge and will remain valid for 14 s minimum (15 s total from falling edge on 1-wire bus). 6) v ih is a function of the external pullup resistor and the v cc supply. 7) 30 nanocoulombs per 72 time slots @ 5.0v. 8) at v cc = 5.0v with a 5k pullup to v cc and a maximum time slot of 120 s. 9) capacitance on the i/o pin could be 800pf when power is first applied. if a 5k resistor is used to pullup the i/o line to v cc , 5 s after power has been applied the parasite capacitance will not affect normal communications. 10) the reset low time (t rstl ) should be restricted to a maximum of 960 s, to allow interrupt signaling, otherwise it could mask or conceal interrupt pulses if this device is used in pa rallel with a ds2404 or ds1994. 11) the optimal sampling point for the master is as close as possible to the end time of the t rdv period without exceeding t rdv . for the case of a read-one time slot, this maximizes the amount of time for the pullup resistor to recover to a high level. for a read-zero time slot, it ensures that a read will occur before the fastest 1-wire device(s) releases the line. 12) the duration of the low pulse sent by the master should be a minimum of 1 s with a maximum value as short as possible to allow time for the pullup resist or to recover the line to a high level before the 1- wire device samples in the case of a write-one time or before the master samples in the case of a read-one time.
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